We propose the serial concatenation of a set of very short LDPC code blocks with components of rate 1. As second component we use a higher order modulation with a sophisticated mapping, a rate-1 convolutional code, or a serial concatenation of both. With this rate-1 component extrinsic information is exchanged between the LDPC code blocks resulting in a very good bit-error rate performance.
The LDPC code blocks and each serial concatenation is separately but simultaneously iteratively decoded. Despite its relative low complexity, simulations show a competitive performance of the proposed system, e.g., compared to the UMTS Turbo code or a sin-
gle, fixed LDPC code. Since the number of LDPC code blocks is flexible, the overall frame size can be adjusted with a high granularity.
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